Regviz

NXP Semiconductors /LPC176x5x /PINCONNECT /I2CPADCFG

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as I2CPADCFG

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/LPC176x5x/PINCONNECT/I2CPADCFG#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (STANDARD)SDADRV0 0 (ENABLED)SDAI2C0 0 (STANDARD)SCLDRV0 0 (ENABLED)SCLI2C0 0RESERVED

SCLDRV0=STANDARD, SDAI2C0=ENABLED, SCLI2C0=ENABLED, SDADRV0=STANDARD

Description

I2C Pin Configuration register

Fields

SDADRV0

Drive mode control for the SDA0 pin, P0.27.

0 (STANDARD): Standard. The SDA0 pin is in the standard drive mode.

1 (FAST_MODE_PLUS): Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode.
SDAI2C0

I 2C filter mode control for the SDA0 pin, P0.27.

0 (ENABLED): Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled.

1 (DISABLED): Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled.
SCLDRV0

Drive mode control for the SCL0 pin, P0.28.

0 (STANDARD): Standard. The SCL0 pin is in the standard drive mode.

1 (FAST_MODE_PLUS): Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode.
SCLI2C0

I 2C filter mode control for the SCL0 pin, P0.28.

0 (ENABLED): Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled.

1 (DISABLED): Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled.
RESERVED

Reserved.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data